Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions

Today's systems on chip (SoCs) require a complex design and verification process. In early stages, high-level debugging of the SoC functionality is feasible TLM (Transaction-Level Modeling) descriptions. To ease such SoC's models, Assertion-Based Verification (ABV) enables runtime temporal properties. last RTL (Register Transfer Level) descriptions hardware blocks expose microarchitectural details. gain confidence in validity system level properties after this TLM-to-RTL synthesis, transaction assertions must be reverifiable models. address that issue, we propose refinement rules for automatic to signal transformation PSL (Property Specification Language, IEEE standard 1850). We sketch architecture prototype tool automates refinement, give some illustrative examples realistic use case.